AS5215
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 6. Electrical System Specifications
Symbol
SF=AP1_
1/AP2_1
V offset1
V offset2
DC offdrift
Parameter
Amplitude ratio mismatch at room
temperature
DC Offset
DC Offset Drift
Condition
Ratiometric to V DD
-40 to 150oC
Min
-2
0.294
0.49
-50
Typ
0.3
0.5
Max
2
0.306
0.51
+50
Unit
%
V / V DD
V / V DD
μV/oC
THD
SR
C LOAD
Total Harmonic Distortion
Slew Rate
Capacitive Load
1
0.2
1000
%
V/μs
pF
6.1 Timing Characteristics
Table 7. Timing Characteristics
Symbol
t1_3
t2_3
t3
t4
t5
t6
t7
t8
t9_3
t10_3
t11
t12
t13_3
Parameter
Chip select to positive edge of DCLK
Chip select to drive bus externally
Setup time command bit
Data valid to positive edge of DCLK
Hold time command bit
Data valid after positive edge of DCLK
Float time
Positive edge of DCLK for last command bit to bus float
Bus driving time
Positive edge of DCLK for last command bit to bus
drive
Data valid time
Positive edge of DCLK to bus valid
Hold time data bit
Data valid after positive edge of DCLK
Hold time chip select
Positive edge DCLK to negative edge of chip select
Bus floating time
Negative edge of chip select to float bus
Setup time data bit at write access
Data valid to positive edge of DCLK
Hold time data bit at write access
Data valid after positive edge of DCLK
Bus floating time
Negative edge of chip select to float bus
Condition
Min
30
0
30
15
-
DCLK/
2+0
DCLK/
2+0
DCLK/
2+0
DCLK/
2+0
-
30
15
-
Typ
Max
-
-
-
-
DCLK/
2+0
-
DCLK/
2+30
-
-
30
-
-
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remark: The digital interface will be reset during the low phase of the CS signal.
www.austriamicrosystems.com/AS5215
Revision 1.11
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